The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. The Select (S) input should be Low for the Add (A plus B) mode and High for the Subtract (A minus B) mode. A Low signal on the asynchronous Master Reset (MR) input clears the sum flip-flop and resets the Carry flip-flop to zero in the Add mode or presets it to one in the Subtract mode.