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Partname: | N74F193D |
Description: | Up/down binary counter with separate up/down clocks, max 125MHz |
Manufacturer: | Philips Semiconductors |
Package: | SO |
Pins: | 16 |
Oper. temp.: | 0 to 70 |
Datasheet: | PDF (148K). Click here to download *) |
The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel Data inputs (D0 - D3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs when the Parallel Load (PL) input is Low. A High level on the Master Reset (MR) input will disable the parallel load gates, override both clock inputs, and set all Q outputs Low. If one of the clock inputs is Low during and after a reset or load operation, the next Low-to-High transition of the clock will be interpreted as a legitimate signal and will be counted. |
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Click here to download N74F193D Datasheet*) |
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