The SerDes uses the recovered downstream clock for upstream serialization (loopback clock), providing optimum PON operation. The CDR frequency reference can be provided by a low-cost 19.44MHz SMD-type crystal or external LVCMOS source, and excellent jitter tolerance supports applications requiring FEC. An integrated burst-enable signal path also simplifies highperformance upstream burst timing. This 3.3V IC is housed in a 8mm x 8mm, 56-lead thin QFN package and operates from -40C to +85C.