The MAX3872 is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48, OC-48 with FEC SONET/SDH and Gigabit Ethernet (1.25Gbps/2.5Gbps) applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by the recovered clock, providing a clean data output. An additional serial input (SLBI) is available for system loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL) output. The MAX3872 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50 back termination on each line. Its jitter performance exceeds all SONET/SDH specifications.