The MAX3273 accepts differential CML-compatible clock and data input signals. Inputs are self-biased to allow AC-coupling. An input data-retiming latch can be enabled to reject input jitter if a clock signal is available. The driver can provide bias current up to 100mA and modulation current up to 60mAP-P with typical (20% to 80%) edge speeds of 59ps. A failure-monitor output is provided to indicate when the APC loop is unable to maintain average optical power. The MAX3273 is available in a 4mm 4mm, 24-pin QFN package, as well as in die form.