The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high, 7.6 effective bits performance at the Nyquist frequency. A fully differential comparator design and decoding circuitry combine to reduce out-ofsequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 1027 clock cycles. Unlike other ADCs, which can have errors that result in false full- or zero-scale outputs, the MAX106 limits the error magnitude to 1LSB. The analog input is designed for either differential or single-ended use with a 250mV input voltage range. Dual, differential, PECL-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX106 devices to increase the effective system sampling rate. The MAX106 is packaged in a 25mm x 25mm, 192-contact Enhanced Super-Ball-Grid Array (ESBGATM), and is specified over the commercial (0C to +70C) temperature range. For a pin-compatible higher speed upgrade, refer to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data sheets.