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Partname: | ZL30409DDB1 |
Description: | T1/E1 system synchronizer with stratum 3 holdover. |
Manufacturer: | Zarlink Semiconductor |
Package: | SOIC(Pb free) |
Pins: | 48 |
Oper. temp.: | -40 to 85 |
Datasheet: | PDF (489K). Click here to download *) |
The ZL30409 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048 MHz, 1.544 MHz, or 8 kHz input reference. |
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![Click here to download ZL30409DDB1 Datasheet](../../../pndecoder/datasheets/ZRLNK/img/000060.gif) Click here to download ZL30409DDB1 Datasheet*) |
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