The XC9500XV family is a 2.5V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XV device supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XV family is designed to work closely with the Xilinx SpartanTM-XL and VirtexTM FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. As shown in Table 1, logic density of the XC9500XV devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500XV family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9500XV architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 3.3V and 2.5V inputs, and the outputs may be configured for 3.3V, 2.5V, or 1.8V operation. The XC9500XV device exhibits symmetric full 2.5V output voltage swing to allow balanced rise and fall times.