The XC17V00 PROM can configure a Xilinx FPGA using the FPGA serial configuration mode interface. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. The XC17V08(1) and XC17V16 PROM can optionally configure a Xilinx FPGA using the FPGA Parallel