The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chips 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. The MCP also incorporates two 16-bit universal bus drivers for input control signals and addresses.