The VSC6108/10/12 are a family of low-jitter clock multiplication and distribution ICs. Each IC uses a phase locked-loop to lock an on-chip low-noise VCO to an off-chip reference frequency. The VCO output can be divided down and is output to 18 differential ECL outputs. The VSC6108/10/12 are packaged in a 10 mm x 10 mm 64-pin plastic quad flat pack and consume less than 2 Watts from a single 3.3V power supply. The VSC6108/10/12 provide high-precision clocks for ATE, instrumentation, telecommunications, datacommunications, and computer system applications where jitter and skew are critical timing parameters. Skew between outputs is less than 50 ps. Jitter is less than 4 ps rms or 25 ps peak-to-peak. Lock time is 10 s.