The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift registers that, when clocked, shift the data toward serial output QH. Parallelin access to each stage is provided by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output QH . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs.