They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of their IC's is synchronous to the rising edge of CK. The clear function of the TC74HC163A is synchronous to CK, while the TC74HC161A is cleared asynchronously. Two enable inputs (ENP and ENT) and CO are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage.