The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power-on, RESET is asserted when the supply voltage (VDD) becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, tdtyp = 180 ms starts after VDD has risen above the threshold voltage VIT.