The TPS310x, TPS311x families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processorbased systems. During power on, RESET is asserted when the supply voltage (VDD) becomes higher than 0.4 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state to ensure proper system reset. The delay time starts after VDD has risen above the VIT. When the VDD drops below the VIT, the output becomes active again.