The TLK4120 is a four channel, multi-gigabit transceiver used in high-speed bidirectional point-to-point data transmission systems. The TLK4120 supports an effective serial interface speed of 0.5 Gbps to 1.3 Gbps per channel, providing up to 1.17 Gbps of data bandwidth per channel. The primary application of the TLK4120 is to provide high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be a printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK4120 can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. The data is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The TLK4120 performs the data parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.3 Gbps. The transmitter latches 18-bit parallel data at a rate based on the supplied reference clock (GTx_CLK). The 18-bit parallel data is internally encoded into 20 bits by framing the 18-bit data with a start and a stop bit. The resulting 20-bit frame is then transmitted differentially at 20 times the reference clock (GTx_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (Rx_CLK). It then extracts the 18 bits of data from the 20-bit wide data resulting in 18 bits of parallel data at the receive data terminals (RDx[0:17]). This results in an effective data payload of 0.45 Gbps to 1.17 Gbps (18 bits data x GTx_CLK frequency). The TLK4120 is designed to be hot plug capable. An on-chip power-on reset circuit holds the Rx_CLK low and places the parallel side output signal terminals, DOUTTxP and DOUTTxN, into a high-impedance state during power up.