These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock. The clear function is initiated by applying a low level to either asynchronous clear (ACLR) or synchronous clear (SCLR). ACLR (direct clear) overrides all other functions of the device, while SCLR overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD) or by the combination of a low level at synchronous load (SLOAD) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR, ALOAD, SCLR, and SLOAD are all high.