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Partname: | SN74LVC112ADBLE |
Description: | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET |
Manufacturer: | Texas Instruments |
Package: | DB |
Pins: | 16 |
Oper. temp.: | -40 to 85 |
Datasheet: | PDF (128K). Click here to download *) |
The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. |
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![Click here to download SN74LVC112ADBLE Datasheet](../../../pndecoder/datasheets/TI/img/001295.gif) Click here to download SN74LVC112ADBLE Datasheet*) |
![](http://www.chipdocs.com/common/img/1x10t.gif) |
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