These hex buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The 'HC365 contain six independent buffers/drivers with dual-gated output-enable (OE1 and OE2) inputs. When OE1 and OE2 are both low, the device passes noninverted data from the A inputs to the Y outputs. If either (or both) output-enable terminal(s) is high, the outputs are in the high-impedance state.