The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OECTM). Improved GTL+ OEC circuits minimize bus settling time and have been designed and tested using several backplane models. Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a 16-slot, 14-inch board with loaded impedance of 33 . VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 . The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous). VTT