The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs will follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output enables do not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.