The eight flip-flops are edge-triggered D-type flip-flops. With the clock-enable (CLKEN) input low, the device enters data on the low-to-high transition of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the eight Q outputs to go low independently of the clock. Buffered output-enable (OE1, OE2, or OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.