The SN74AS131A is a 3-line to 8-line decoder/demultiplexer with registers on the three address inputs. When the clock (CLK) input goes from low to high, the device acts as a decoder/ demultiplexer and the address present at the select (A, B, and C) inputs is stored in the registers. Further address changes are ignored until the next rising transition of CLK. The output-enable (G1, G2) inputs control the state of the outputs independently of the select or CLK inputs. All of the outputs are high unless G1 is high and G2 is low. This device is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.