The data-flow control logic is designed to allow glitch-free data transmission. When preset (PRE) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To leave the high-impedance state, both PRE and SELEN must be low and a clock pulse must be applied. To ensure the high-impedance state during power up or power down, PRE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16409 is characterized for operation from 40C to 85C.