The SN74ALVC3651 is a high-speed, low-power, CMOS, synchronous FIFO memory that supports clock frequencies up to 100 MHz and has read access times as fast as 6.5 ns. The 2048 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion also is possible in word depth. The SN74ALVC3651 is a synchronous FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage, synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage, synchronized to CLKB. Offset values for AF and AE are programmed from port A or through a serial input. The SN74ALVC3651 is characterized for operation from 0C to 70C. For more information on this device family, see the following application reports: