The SN65LVDS308 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS308 receiver contains one shift register to load 30 bits from two serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.