The SN65LVDS307 supports three power modes (shutdown, standby, and active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock, PCLK, and generates an internal high-speed clock at the line rate of the data lines. The parallel data are latched on the rising or falling edge of PCLK, as selected by the external control signal CPOL. The serialized data is presented on the serial outputs D0 and D1, together with a recreated PCLK that is generated from the internal high-speed clock and output on CLK. If PCLK stops, the device enters a standby mode to conserve power.