The dual 4-bit latches are transparent D-type. When the latch enable input (1C or 2C) is high, the Q outputs will follow the data (D) inputs in inverted form, according to the function table. When the latch enable input is taken low, the outputs will be latched. When PRE goes low, the Q outputs go low independently of the clock. The outputs are in a high-impedance state when OC (output control) is at a high logic level.