The DAC5675-EP is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675-EP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675-EP has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675-EP well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs). The DAC5675-EP operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW at fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675-EP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD. The DAC5675-EP comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675-EP and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675-EP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing. The DAC5675-EP has been specifically designed for a differential transformer-coupled output with a 50- doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD- 1 to AVDD + 0.3 V.