The FCT377T has eight triggered D-type flip-flops with individual D inputs. The common buffered clock inputs (CP) loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The outputs are designed with a power-off disable feature to allow for live insertion of boards.