These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. The output buffers are designed with a power-off disable feature to allow live insertion of boards. THE CY74FCT163501 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors, as well as provides for minimal undershoot and reduced ground bounce. The CY74FCT163501 is ideal for driving transmission lines. The CY74FCT163H501 is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input's last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.