The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2510 is characterized for operation from 0C to 85C. For application information see the application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking (SSC) (SCAA039).