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Partname:CDCM1804RGERG4
Description:1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider
Manufacturer:Texas Instruments
Datasheet:PDF (448K).
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The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 x 27 = 54. See Table 1 for details.

Click here to download CDCM1804RGERG4 Datasheet
Click here to download CDCM1804RGERG4 Datasheet
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