The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50- transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from -40C to 85C. For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.