The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem and Redwood logic interface using a reference clock input with or without spread-spectrum modulation. Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an off-the-shelf solution for a broad range of high-performance interface applications. The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a logical low at the input of the EN pin. An output is enabled when EN is high and a value of 1 is in its serial interface register (RegARegD). The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to high impedance. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Rambus, XDR are trademarks of Rambus Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.