The CDC9171 generates all output frequencies from an 18.432-MHz crystal. The 18.432-MHz (FCLK1) reference clock output is buffered from the integrated oscillators. Two integrated phase-lock loops (PLL) synthesize the 27-MHz (FCLK2, FCLK3) and the 33.868-MHz (FCLK4) reference clock outputs from the 18.4320-MHz crystal. The oscillator and PLLs can be bypassed in the TEST mode. When TEST is high, input 1X1 is buffered to all outputs. All clock outputs provide low-jitter clock signals for reliable clock operation. PWRDN is used to disable the PLLs and output buffers. When low, PWRDN disables the integrated PLLs and forces all outputs to a logic-low state. Because the CDC9171 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the 1X1 input and upon activation, following the transition of PWRDN to a logic-high state. FUNCTION TABLE