The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock system design for PC motherboards. The CDC913 consists of a crystal oscillator, two phase-locked loops (PLL), and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal. The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input and buffered out from the PCICLK, CPUCLK, and REFCLK outputs. Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are enabled. Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, and following any changes to the SELn inputs.