The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC582 operates at 3.3-V VCC. The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN) signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized to the same frequency as the clock (CLKIN and CLKIN) inputs.