The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring output signals at both the primary clock frequency and one-half the primary clock frequency. This device contains two banks that fan out one input to three same-frequency outputs and one bank that fans out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the frequency of their clock (2A) input. When the output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to the high level. When a bank's OE input is high, the outputs are in the high-impedance state. The CDC330 is characterized for operation from 0C to 70C. FUNCTION TABLES