The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input. The CDC305 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver when a divide-by-two function is required. The CDC305 is characterized for operation from 0C to 70C. FUNCTION TABLE