The clear function is initiated by applying a low level to either asynchronous clear (ACLR) or synchronous clear (SCLR). Asynchronous (direct) clearing overrides all other functions of the device, while synchronous clearing overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by holding load (LOAD) low during a positive-going clock transition. The counting function is enabled only when enable P (ENP) and enable T (ENT) are low and ACLR, SCLR, and LOAD are high. The up/down (U/D) input controls the direction of the count. These counters count up when U/D is high and count down when U/D is low.