These counters are fully programmable in that they may be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when power is applied, it progresses to the normal sequence within two counts as shown in the state diagram. The clear function for the 74AC11162 is synchronous, and a low level at the clear (CLR) input drives all four of the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs).