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Partname:74AC11112D
Description:Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
Manufacturer:Texas Instruments
Datasheet:PDF (93.8K).
Click here to download *)

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

Click here to download 74AC11112D Datasheet
Click here to download 74AC11112D Datasheet
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