The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted in a less expensive processor that can be designed into systems currently using costly bit-slice processors.