The peak current is detected by monitoring voltage at external sense resistors connected to RSENSE1-3. The switching MOSFET is turned off when the corresponding current sense signal exceeds the reference voltage applied at REF1-3 (in the case of normal output signal polarity). Beginning of the next switching cycle is determined by the external clock signal received at the CLK input. All three channels operate at a switching frequency of 1/6 of the external clock frequency and positioned 120 out-of-phase for the purpose of input and output ripple current reduction. Each channel is protected from an output short circuit condition. When an over-current condition is detected in the output switch (RSENSE1-3), the corresponding channel shuts down for 200us. HV9980 recovers automatically, when the short circuit condition is removed. Each current sense input (CS1-CS3) is equipped with a leading edge blanking delay to prevent false triggering of the current sense comparators due to circuit parasitics.