The device is loaded at up to 30MHz using six parallel data inputs, achieving an effective 180MHz data load rate. A direction pin (DIR) is provided to control the data load sequence. Once data is latched into the output latches, the outputs will be controlled based on the latch contents, polarity (POL) pin and output enable (OE) pin inputs. All outputs may be temporarily forced high by asserting a `low' on the OHB input. Alternatively, all outputs may be temporarily forced low by asserting a `low' on the OLB input. This versatility allows the outputs to be individually controlled, all set high or low, or all set to a highZ state.