The TSA1204 is specifically designed for applications requiring very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction to provide excellent static linearity and over 11.2 effective bits at Fs=20Msps, and Fin=10MHz. For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. Each ADC outputs are multiplexed in a common bus with small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially driven.