The STSMIA832 receiver converts the subLVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL. The device recognizes the SMIA 32 bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 82 MHz) is transmitted in parallel with data. Output data are rising-edge strobes. This chipset is an ideal means to link mobile camera modules to Baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces the Maximum Current Consumption to 10 A making this device ideal for portable applications like Mobile Phone and Portable Battery Equipment. A configurable input (Class_Sel) is provided to select different CLASS (0 or 1,2) mode inside the SMIA STD specifications.