The following malfunctions are known in this step: 2.1 ST_PWRDN.1: EXECUTION OF PWRDN INSTRUCTION WHILE NMI PIN IS HIGH When PWRDN instruction is executed while NMI pin is at a high level, power-down mode should not be entered, and the PWRDN instruction should be ignored. However, under the conditions described below, the PWRDN instruction may not be ignored, and no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This problem will only occur in the following situations: 1) the instructions following the PWRDN instruction are located in an external memory, and a multiplexed bus configuration with memory tristate waitstate (bit MTTCx= 0) is used, 2) the instruction preceding the PWRDN instruction writes to external memory or an XPeripheral (XRAM, CAN), and the instructions following the PWRDN instruction are located in external memory. In this case, the problem will occur for any bus configuration. Note: the on-chip peripherals still work correctly: if the Watchdog Timer is not disabled, it will reset the device upon an overflow. Interrupts and PEC transfers, however, can not be processed. If NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered.