The following malfunctions are known in this step: 2.1 - PWRDN.1 - Execution of PWRDN Instruction When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRDCFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the PWRDN instruction is ignored.